The growing demand for higher bit rate communication from radio frequency (RF) transceivers mandates the use of modulation code schemes (MCS) on the transmit side, that has high peak to average power ratio (PAPR) signal characteristic.
The high PAPR necessitates the use of a linear power amplifier (PA) characterized with poor efficiency.
The lack of available frequencies pushes the linear RF PA to higher frequencies and higher signal Band width (BW) which necessitates the use of fabrication technologies with transistor that have high Transition Frequency (FT) characteristic.
For CMOS technology, the higher (FT) is achieved by means of smaller and smaller geometry and lower supply voltage and threshold voltage (VT).
Trying to mitigate the poor efficiency in linear PA and coping with smaller dynamic range (DR) due to lower supply voltage in advanced CMOS technologies, designers tend to bias the PA transistors close to VT or even sub threshold operating condition, which makes the design more sensitive to process voltage and temperature (PVT) variations.
The use of minimum channel length in the PA transistors magnifies the sensitivity to PVT variation resulting in variant PA operation.
If constant current and gm is maintained in the PA transistors, PA sensitivity would greatly reduce.
Maintaining constant current and gm (conductance) on the PA must be done with minimal intrusion to the PA, in order to avoid influencing PA characteristics.